One kind of MOS static RAMs uses a complete CMOS type memory cell. As shown in FIG. 2, this CMOS type memory cell comprises a flip-flop circuit having a first inverter including driver transistor Q.sub.1 and load transistor Q.sub.2 and a second inverter including driver transistor Q.sub.3 and load transistor Q.sub.4 in which an input of one inverter is connected with an output of the other inverter, and a pair of access transistors Q.sub.5 and Q.sub.6 for data communication with an exterior of the cell. In FIG. 2, WL denotes a word line; BL and BL' denote bit lines, respectively; and V denotes a power supply voltage.
In recent years, frequently, the load transistors Q.sub.2 and Q.sub.4 in the above complete CMOS type memory cell are each formed by a p-channel thin film transistor (TFT: Thin Film Transistor). FIG. 3 shows a cross-section of the main part of the p-channel TFT serving as a load transistor. In FIG. 3, reference numeral 101 denotes an interlayer insulation film; 102 denotes a gate electrode; 103 denotes a gate insulating film; and 104 denotes a polycrystalline silicon (hereinafter referred to as polysilicon) film. It should be noted that the polysilicon film 104 is formed so as to cover an end portion of the gate electrode 102. The polysilicon film 104 includes a p.sup.+ -type source region 105 and a p.sup.+ -type drain region 106. The gate electrode 102, source region 105 and drain region 106 constitute a p-channel TFT serving as a load transistor.
In known CMOS type memory cell, as shown in FIG. 3, the drain region 106 of the p-channel TFT serving as a load transistor is usually formed so that its end portion is close to the end portion of the gate electrode 102. For this reason, hot carriers are generated during operation by the electric field between the end portion of the gate electrode 102 and the drain region 106, resulting in deterioration of the characteristic of the p-channel TFT as a load transistor.